Espressif Systems /ESP32-P4 /SPI0 /SPI_SMEM_TIMING_CALI

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Interpret as SPI_SMEM_TIMING_CALI

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SPI_SMEM_TIMING_CLK_ENA)SPI_SMEM_TIMING_CLK_ENA 0 (SPI_SMEM_TIMING_CALI)SPI_SMEM_TIMING_CALI 0SPI_SMEM_EXTRA_DUMMY_CYCLELEN 0 (SPI_SMEM_DLL_TIMING_CALI)SPI_SMEM_DLL_TIMING_CALI

Description

MSPI external RAM timing calibration register

Fields

SPI_SMEM_TIMING_CLK_ENA

For sram, the bit is used to enable timing adjust clock for all reading operations.

SPI_SMEM_TIMING_CALI

For sram, the bit is used to enable timing auto-calibration for all reading operations.

SPI_SMEM_EXTRA_DUMMY_CYCLELEN

For sram, add extra dummy spi clock cycle length for spi clock calibration.

SPI_SMEM_DLL_TIMING_CALI

Set this bit to enable DLL for timing calibration in DDR mode when accessed to EXT_RAM.

Links

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